Design of a ROIC for scanning type HgCdTe LWIR focal plane arrays

Design of a silicon readout integrated circuit (ROIC) for LWIR HgCdTe Focal Plane is presented. ROIC incorporates time delay integration (TDI) functionality over seven elements with a supersampling rate of three, increasing SNR and the spatial resolution. Novelty of this topology is inside TDI stage; integration of charges in TDI stage implemented in current domain by using switched current structures that reduces required area for chip and improves linearity performance. ROIC, in terms of functionality, is capable of bidirectional scan, programmable integration time and 5 gain settings at the input. Programming can be done parallel or serially with digital interface. ROIC can handle up to 3.5V dynamic range with the input stage to be direct injection (DI) type. With the load being 10pF capacitive in parallel with 1MΩ resistance, output settling time is less than 250nsec enabling the clock frequency up to 4MHz. The manufacturing technology is 0.35μm, double poly-Si, four-metal (3 metals and 1 top metal) 5V CMOS process

Realization of a ROIC for 72x4 PV-IR detectors

Silicon Readout Integrated Circuits (ROIC) for HgCdTe Focal Plane Arrays of 1x4 and 72x4 photovoltaic detectors are represented. The analog circuit blocks are completely identical for both, while the digital control circuit is modified to take into account the larger array size. The manufacturing technology is 0.35μm, double poly-Si, three-metal CMOS process. ROIC structure includes four elements TDI functioning with a super sampling rate of 3, bidirectional scanning, dead pixel de-selection, automatic gain adjustment in response to pixel deselection besides programmable four gain setting (up to 2.58pC storage), and programmable integration time. ROIC has four outputs with a dynamic range of 2.8V (from 1.2V to 4V) for an output load of 10pF capacitive in parallel with 1MΩ resistance, and operates at a clock frequency of 5 MHz. The input referred noise is less than 1037 μV with 460 fF integration capacitor, corresponding to 2978 electrons

Realization of readout integrated circuit (ROIC) for an array of 72x4, P-on-N type HgCdTe long wave infrared detectors

Infrared Focal Plane Arrays (IRFPAs) are important and high-tech systems, which are used in many strategic applications, such as medical imaging, missile guidance, and surveillance systems. The most important building blocks of IRFPAs are detectors and Readout Integrated Circuit (ROIC). Both of them need careful design and implementation for the overall system to be succesful. Detector part produces the photon induced current and sent to the input of ROIC. Detector design and fabrication determines the operating wavelength and main noise performance of the imaging system. On the other hand, ROIC is the interface element between the detector and microcomputer of the IRFPA system, and determines important performance parameters of the overall system; such as linearity, dynamic range, injection efficiency, noise performance (less effective than detector), and power consumption. Therefore it is important to design and implement a ROIC, that fits best to the desired application. In this thesis, a CMOS ROIC is designed and implemented for scanning type of 72×4 Pon- N HgCdTe detector array in 0.35 μm, 4 metal 2 poly AMS CMOS process. Current Mirror Integration (CMI) is used as the unit cell of the ROIC. For the signal processing, Time Delay Integration (TDI) over 4 elements with an optical supersampling rate of 3 is used for improved Signal-to-Noise Ration (SNR). The designed and implemented ROIC has the properties of bidirectional scanning, variable integration time, adjustable gain settings, bypass functionality, automatic gain adjustment, and pixel selection/deselection functionality. ROIC is programmable through a serial and a parallel interface. Gain settings, TDI scanning direction, information of mulfunctioning pixels, ROIC operation mode (test or TDI) can be programmed by using these interfaces. Operating frequency of the ROIC is up to 5 MHz, while the dynamic range is 2.8 V

Digital pixel readout integrated circuit architectures for LWIR

This paper presents and discusses digital pixel readout integrated circuit architectures for long wavelength infrared (LWIR) in CMOS technology. Presented architectures are designed for scanning and staring arrays type detectors respectively. For scanning arrays, digital time delay integration (TDI) is implemented on 8 pixels with sampling rate up to 3 using CMOS 180nm technology. Input referred noise of ROIC is below 750 rms electron meanwhile power dissipation is appreciably under 30mW. ROIC design is optimized to perform at room as well as cryogenic temperatures. For staring type arrays, a digital pixel architecture relying on coarse quantization with pulse frequency modulation (PFM) and novel approach of extended integration is presented.. It can achieve extreme charge handling capacity of 2.04Ge(-) with 20 bit output resolution and power dissipation below 350 nW in CMOS 90nm technology. Efficient mechanism of measuring the time to estimate the remaining charge on integration capacitor in order to achieve low SNR has employed

Low-power LVDS for digital readout circuits

This paper presents a mixed-signal LVDS driver in 90 nm CMOS technology. The designed LVDS core is to be used as a data link between Infrared Focal Plane Array (IRFPA) detector end and microprocessor input. Parallel data from 220 pixels of IRFPA is serialized by LVDS driver and read out to microprocessor. It also offers a reduced power consumption rate, high data transmission speed and utilizes dense placement of devices for area efficiency. The entire output driver circuit including input buffer draws 5mA while the output swing is 500mV at power supply of 1.2V for data rate of 6.4Gbps. Total LVDS chip area is 0.79 mm(2). Due to these features, the designed LVDS driver is suitable for purposes such as portable, high-speed imaging

Cryogenic measurements of a digital pixel readout integrated circuit for LWIR

This paper presents and discusses the cryogenic temperature (77K) measurement results of a digital readout integrated circuit (DROIC) for a 32x32 long wavelength infrared pixel sensor array designed in 90nm CMOS process. The chip achieves a signal-to-noise ratio (SNR) of 58dB with a charge handling capacity of 2.03Ge- at cryogenic temperature with 1.3mW of power dissipation. The performance of the readout is discussed in terms of power dissipation, charge handling capacity and SNR considering the fact that the process library models are not optimized for cryogenic temperature operation of the Metal-Oxide-Semiconductor (MOS) devices. These results provide an insight to foresee the design confrontations due to non-optimized device models for cryogenic temperatures particularly for short channel devices

A low-power CMOS readout IC with on-chip column-parallel SAR ADCs for microbolometer applications

A readout IC (ROIC) designed for high temperature coefficient of resistance (TCR) SiGe microbolometers is presented. The ROIC is designed for higher Ge content SiGe microbolometers which have higher detector resistance (∼1MΩ) and higher TCR values (∼%5.5/K). The ROIC includes column SAR ADCs for on-chip column-parallel analog to digital conversion. SAR ADC architecture is chosen to reduce the overall power consumption. The problem of resistance variation across the bolometers which introduce fixed pattern noise is addressed by setting a tunable reference resistor shared for each column which can be calibrated offline to set the common-mode level. Moreover, column non-uniformity has been reduced through comparator offset compensation in the SAR ADC. The columnwise architecture in this work reduces the number of integrators needed in the architecture and enables 17×17 μm2 pixel sizes. The prototype has been designed and fabricated in 0.25-μm CMOS process

Diagnostic performance and interobserver agreement of CO-RADS: evaluation of classification in radiology practice

PURPOSEWe aimed to evaluate the use of the COVID-19 reporting and data system (CO-RADS) among radiologists and the diagnostic performance of this system.METHODSFour radiologists retrospectively evaluated the chest CT examinations of 178 patients. The study included 143 patients with positive reverse transcriptase-polymerase chain reaction (RT-PCR) test results and 35 patients whose RT-PCR tests were negative but whose clinical and/or radiological findings were consistent with COVID-19. Fleiss’ kappa (κ) values were calculated, and individual observers’ scores were compared. To investigate diagnostic efficiency, receiver operating characteristic (ROC) curves were calculated for each interpreter.RESULTSThe interpreters were in full agreement on 574 of 712 (80.6%) evaluations. The common Fleiss’ κ value of all the radiologists combined was 0.712 (95% confidence interval [CI] 0.692–0.769). A reliable prediction on the basis of RT-PCR and clinical findings indicated the mean area under the curve (AUC) of Fleiss’ κ value as 0.89 (95% CI 0.708–0.990). General interpreter agreement was found to range from moderate to good.CONCLUSIONThe interpreter agreement for CO-RADS categories 1 and 5 was reasonably good. We conclude that this scoring system will make a valuable contribution to efforts in COVID-19 diagnosis. CO-RADS can also be of significant value for the diagnosis and treatment of the disease in cases with false-negative PCR results

A DROIC based on PFM ADCs employing over-integration for error shaping

This paper presents a digital readout integrated circuit (DROIC) for small pitch medium-wave infrared (MWIR) starring focal plane arrays (FPAs). To overcome the limited in-pixel resolution of such DROICs, the concept of error shaping is introduced in pulse frequency modulation (PFM)-based pixels. Multiple integration operations are performed in a single frame and the residue charge from each integration phase is retained and injected into the next charge packet. This over-integration routine provides a high pass noise transfer function (NTF) equivalent to what is obtained in a first order sigma delta modulator. The concise structure of a PFM analog-to-digital converter (ADC) lends itself well to such an operation inside the pixel, while consuming low power. Along with a theoretical analysis of the technique, a prototype based on a 16x16 array and sinc decimation filters is developed to demonstrate the performance of the proposed DROIC. With an in-pixel resolution of 5 bits and over-integration ratio (OIR) of 128, 395 noise electrons are demonstrated at full-well fill from the test array fabricated in a 90 nm bulk-CMOS process